1. Field of the Invention
The present invention relates to an apparatus and a method to time multiplex logic in a physical design domain instead of multiple instantiation.
2. Description of the Related Art
As computer performance has increased in recent years, the demands on computer networks has significantly increased; faster computer processors and higher memory capabilities need networks with high bandwidth capabilities to enable high speed transfer of significant amounts of data. The well-known Ethernet technology, which is based upon numerous Institute of Electrical and Electronic Engineers (IEEE) Ethernet standards, is one example of computer networking technology which has been able to be modified and improved to remain a viable computing technology.
Switches, as they relate to computer networking and to Ethernet, are hardware-based devices which control the flow of data packets or cells based upon destination address information which is available in each packet. A properly designed and implemented switch or module should be capable of receiving a packet and switching the packet to an appropriate output port at what is referred to wirespeed or linespeed, which is the maximum speed capability of the particular network. As speed has increased, design constraints and design requirements have become more and more complex with respect to following appropriate design and providing a low cost, commercially viable solution. For example, conventional Dynamic Random Access Memory (DRAM) is relatively slow, and requires hardware-driven refresh. The speed of DRAMs, therefore, as buffer memory in network switching, results in valuable time being lost, and it becomes almost impossible to operate the switch or the network at linespeed. Additionally, as network modules have become more and more complicated with respect to requiring rules tables and memory control, an increase in the amount of hardware is necessary to enable higher processing speed and the various chips to communicate with each other. A network module is needed in which logic components may be multiplexed thereby significantly reducing the amount of logic needed.